1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to an electrostatic discharge protection circuit for a semiconductor device.
2. Description of Related Art
In semiconductor devices, an electrostatic discharge protection circuit for protecting an internal circuit from the ESD (electrostatic discharge) surge applied to Input/Output pads is mounted. FIG. 1 shows a circuit diagram of a general configuration of a semiconductor device mounting an electrostatic discharge protection circuit.
The semiconductor device shown in FIG. 1 includes a VDD pad 101, a signal input pad 102, a GND pad 103, a high potential power source line 104, a signal line 105, a low potential power source line (ground line) 106, an output circuit 107, and an ESD protection elements 111, 112. The output circuit 107 is a circuit used for outputting a signal to an outside of the semiconductor device, and includes a final stage output driver 108 and a predriver 109. The final stage output driver includes a PMOS transistor P1 and an NMON transistor N1. The predriver 109 includes a PMOS transistor P2 and an NMOS transistor N2. The final stage output driver 108 drives the signal output pad 102 in a range from the GND potential to the VDD potential correspondingly to the value of a signal to be outputted to an outside. The predriver 109 drives a gate of the NMOS transistor N1 in response to a control signal supplied from an internal circuit (not shown). Though not shown, a predriver having a similar configuration as the predriver 109 is connected to a gate of the PMOS transistor P1. The ESD protection elements 111, 112 have a function to discharge an ESD surge inputted to the signal output pad 102 to the high potential power source line 104 or a low potential power source line 106 to protect the output circuit 107.
The off transistor is a typical element used for the ESD protection circuits 111, 112. The off transistor is a MOS transistor whose gate potential is fixed such that the transistor becomes an off-state under a normal operation, and discharges the ESD surge by a parasitic bipolar operation. Generally, when an NMOS transistor is used as the off transistor, the drain of the NMOS transistor is connected to a signal line, and the source and the drain thereof are connected to the low potential power source line (ground line). On the other hand, when a PMOS transistor is used as the off transistor, the drain of the PMOS transistor is connected to a signal line, and the gate and the source thereof are connected to the high potential power source line. The off transistor discharges the ESD surge by a parasitic bipolar operation when the ESD surge is applied to the drain thereof. By this principle, the off transistor functions effectively as an ESD protection element.
However, in a circuit configuration using an ESD protection element utilizing a parasitic bipolar operation, the design window becomes smaller in accordance with the downsizing of transistors. FIG. 2 is a graph showing a relationship between the breakdown voltage VBD of the gate insulating film and the clamp voltage Vclamp (the voltage during a discharge by a parasitic bipolar operation) when an NMOS transistor is operated by a parasitic bipolar operation. Whereas the breakdown voltage VBD rapidly decreases with the decrease of the film thickness of the gate insulating film, the claim voltage Vclamp does not decrease. As a result, the design window of an ESD protection circuit becomes smaller in association with the decrease of the film thickness of a gate insulating film.
As a means for solving such a problem, a circuit configuration is known in which a thyristor is used as an ESD protection element and a trigger current is supplied by a trigger element which operates at a low voltage (referring patent document 1: Japanese Patent Application Publication JP-P2008-218886A, and non-patent document 1: EOS/ESD Symposium 07-376, “A Low-Leakage SCR Design Using Trigger-PMOS Modulations for ESD Protection”). FIG. 3 shows a circuit diagram of an electrostatic discharge protection circuit of such a circuit configuration. The electrostatic discharge protection circuit in FIG. 3 includes: a VDD pad 201; a signal pad 202; a GND pad 203; a high potential power source line 204; a signal line 205; a low potential power source line (ground line) 206; a thyristor 207; a diode for ESD protection D1; and a PMOS transistor P1.
In the electrostatic discharge protection circuit of FIG. 3, the PMOS transistor P1 functions as a trigger element which supplies a trigger current to the thyristor 2047. In detail, when an ESD surge is applied to the signal pad 202, the PMOS transistor P1 turns on, and a trigger current is supplied to the thyristor 207. The PMOS transistor P1 supplies a trigger current not by a parasitic bipolar operation, but by a normal MOS transistor operation. Accordingly, the electrostatic discharge protection circuit in FIG. 3 can be operated at a low voltage (concretely, the sum of the forward voltage of the PN junction in the thyristor 2047 and the threshold voltage of the MOS transistor). In addition, because the thyristor 207 is used, it is possible to flow a large current, so that the capacity of the electrostatic discharge protection is high.